1. FIELD OF THE INVENTION
This invention is concerned with a new integrated circuit package and in particular to such a package which enables the integrated circuits to be optically interconnected and which handles optical inputs and outputs in parallel.
2. DESCRIPTION OF THE PRIOR ART
The processing speed of processors has been increasing at an astounding pace in recent years, and the demand for higher-speed processors is also growing. Efforts to meet this demand have been concentrated not only on manufacturing higher-speed integrated circuits (ICs) but also on improving processor architectures. Increasing processing speed by improving individual processor architecture, however, seems to approach its own limits.
More recently, the need for higher processing speed is being met by providing a variety of parallel processing systems. In these parallel systems, if communications among processors are inadequate, the functions of the parallel processors system cannot be fully accomplished. Thus, complex, multiple path inter-board wiring is needed, which increases the cost of the processors. Attempts has been made to construct an architecture that divides functions within a processor, but, as yet, none of these architectures has reached commercial usefulness.
A processor architecture has been proposed which incorporates the concept of a multi-chip module (MCM) in a U.S. patent application filed on Mar. 25, 1992, Ser. No. 07/857,626 under the title of "PARALLEL DIGITAL PROCESSING SYSTEM USING OPTICAL INTERCONNECTIONS." That is to say, this proposal represents the separation of the processor section from the control-memory section. In this architecture, the processor section uses a group of processor units arranged in an array on a single chip. The architecture can easily accomplish the mutual communications among the processor units. The above-mentioned application has also proposed a system of inputting a large number of data and control signals into the processor chip in the form of optical signals.
In general, there are several means for implementing the parallel operation of processors, such as upgrading IC-chip architecture, and improving communications between chips. In order to enhance IC-chip architecture, or use wider-bandwidth buses for communications, it is desirable to improve the characteristics of chip packages, and such efforts are now being vigorously pursued.
As a result of the dramatic progress of semiconductor device fabrication technology, the number of transistors fabricated on a chip has been greatly increased. Miniaturization of transistors has also brought about reductions in the gate length of MOS transistors and in the electron diffusion layers of bipolar transistors, which has resulted in an increase in processing speed. These advances have permitted ICs to operate using substantially increased clock rates.
To effectively use these high-speed processing operations, it is desirable to allow data or control signals to be transferred at high-speed when the occasion demands. The demand for higher-speed and larger numbers of data transmission paths still remains strong even though the need for high-speed processing has already been partially satisfied by providing cache memories in the systems.
Development efforts have been rapidly stepped up to increase the number of input/output ports for a chip as the most immediate means for implementing these demands. That is, development efforts are being directed towards improving existing chip packages which hold chips and connect them to external circuits, in addition to developing entirely new packages.
Efforts are also being directed towards increasing the number of terminals (i.e., pins) on pin grid array (PGA) packages, or leads on quad flat packages (QFP). A simple method for increasing the number of terminals on a chip package is to increase the area on which pins are mounted. This has not been effective, however, because it inevitably involves an increase in package size which reduces the numher of components that can be mounted on a fixed-size circuit board and, so, is not always effective as a method of reducing the size of systems.
Another improvement which is being energetically pursued is to increase terminal density on a package to as fine as 0.3 mm pitch on PGA packages. A method of mounting pins on the entire bottom surface of the package has also been attempted. In the field of QFPs, there is a continuing challenge to reduce the outer pitch of the leads. Needless to say, improvement efforts are also being made concerning the technology of soldering leads on circuit board pads.
Now, typical characteristics required of IC packages will be briefly explained. First comes the need to increase the number of terminals to keep up with the ever-increasing degree of transistor integration, as noted earlier; second, the need to minimize the delay for the signals entering or leaving a chip; third, the need to match the thermal expansion coefficients of chip and package materials; fourth, the need to meet the high heat dissipation requirement of the larger IC's; fifth, the need to simplify interconnection to other devices (circuit boards); sixth, the need for smaller systems, or downsizing; and last the need to maintain sufficient reliability.
The reliability of a chip involves various requirements: above all, positive and stable interconnections to other devices, and also positive and stable sealing of packages which require sealing.
Improvements are constantly under way on the aforementioned PGA and QFP packages to meet these requirements. New chip package mounting methods include the bare-chip package mounting, such as the chip-on-board (COB) and the tape carrier package (TCP) techniques. The COB mounting method interconnects chips directly onto a circuit board or via carriers without packaging other than an encapsulant (glob top). The most COB common terminal connection being flip-chip bonding, although wire bonding is also commonly used.
The flip-chip bonding technique, using grid arrays of solder bumps, can accommodate probably the largest number of terminals, but this technique also requires utmost care in soldering. In addition, it is desirable to pay careful consideration to the distribution and matching of mechanical and thermal external forces between the chip, the chip carrier and the circuit board. The mechanical external forces, such as those caused by thermal expansion, are applied directly to the chip in this process.
The TCP technique relates to tape automated bonding (TAB). This technique uses a carrier made of a plastic film, and bare chips having bumps which are bonded directly to the inner leads of metal foil interconnects on the film carrier. The TCP process has characteristics compatible to multi-pin connections as in the case of the COB mounting, and packages produced are relatively small, light-weight and thin. The TCP process can be used to realize fine-pitch fabrication and reduced inner bonding pad pitches. This is so because the process makes submil (i.e. less than 0.001 in.) inner lead pitch fabrication possible by using an electrically conductive foil bonded to a plastic film.
For the most part, in COB, TCB and other bare-chip package mounting techniques, all terminals are bonded either en bloc or automatically in rapid succession, to produce a bond strength which is several times higher than wire bonding. This advantage may pose a disadvantage, however, because chips, once bonded into circuits, may be hard to remove, making it difficult to repair the device.
With the state-of-the-art technology, the number of terminals that can be fabricated is less than about 1000, and chips having 200 to 300 terminals are more commonly used.
Improvements of processor performance are being continually pursued to such an extent that chips having several ALUs (arithmetic and logic units) are commercially available. To effectively use these new processors, however, it is desirable to provide multiple high speed parallel signal input/output ports.